The present invention is directed to a method of employing a processing apparatus in a host device for full duplex communications through a plurality of ports where the processing apparatus has one timer and executes functions in response to a program of instructions.
It is desirable for a communication device to have the capability to send and receive information simultaneously, i.e. to have full duplex communications, from each input/output (access) port of the device. The output of the device can be controlled; however, there is no control exercisable over arrival times of input signals. Prior art devices have utilized microprocessing units, such as an 8051 micro-processor unit, which has two timers and a serial in/serial out port. With such an arrangement one timer is used in conjunction with a UART (Universal Asyncronous Receiver/Transmitter), which UART was dedicated to the serial in/serial out port; the second timer was dedicated to the remaining access port to control its operation.
At present day prices a micro-processor unit of the 8051 type is nearly 21/2 times the price of a type 8048/8049 micro-processor unit. The type 8048/8049 micro-processor unit is a cheaper unit because it has a smaller program memory, only one timer and no serial in/serial out port with an associated UART. No prior art devices or methods are know which would enable use of the simpler and less expensive type 8048/8049 MPU (micro-processor unit) to provivde full duplex communicates through each of two access ports.
The present invention provides a method which enables use of a micro-processor unit having one timer and a plurality of access ports for full duplex communications through each of those access ports. Thus, significant cost savings over prior art devices in construction of communication devices can be achieved through use of the present invention.